Robust Cache Coherence Protocol Verification with Inferno EECS 578 Project Report Team FLY - Bee

Fault tolerant architectures are emerging to guarantee the reliable functionality of vulnerable silicon devices. However, the growing complexity of the coherence protocol and Network-on-Chip (NoC) design come to be a big challenge to presilicon verification. In this work, we implemented a custom designed robust MESI and directory based cache coherence protocol in System Verilog and practiced with Inferno a software tool that operates on a logic simulation trace and automatically extracts transactions of the RTL design to evaluate the tool’s help on accelerating the verification process. Experiments show that comparing with verification approaches that only use waveform viewer based debugging tools, adding Inferno into the verification process can effectively reduce the time and efforts verification engineers need to make to detect and locate potential bugs in the design. We also summarize our user experience with Inferno and present suggestions both to Inferno users and developers in this paper.